Intel "Lynx Point" 8-series chipset, which will form the foundation of 4th Generation Core processors in the LGA1150 package, codenamed "Haswell", was detailed in a leaked company slide. A slightly older report this week focused on Haswell chips having DirectX 11.1 graphics, and a reorganized display output logic that sees digital display outputs being wired to the processor package, while analog display outputs being routed to the chipset. This chipset talks to the processor's embedded graphics controller over a slightly less functional Flexible Display Interface (FDI).
Lynx Point chipset is a platform controller hub (PCH), much like all the Intel client-platform chipsets released since P55. A crude way to define its function would be to call it a "glorified southbridge", which handles all the connectivity of the system, while lacking the main PCI-Express root complex of the system to which graphics cards are ideally connected, as that's relocated to the CPU package. The PCH does have a narrower 8-lane PCIe hub, but to wire out x1 and x4 expansion slots, and onboard controllers. The Lynx Point chipset connects to the processor primarily over DMI, although the slide doesn't detail the DMI bandwidth. Most likely, it's similar to Cougar Point's 4 GB/s. Lynx Point also lacks a supplementary 4 GB/s PCIe link from the processor that's found on X79 chipset.
Getting into the fine print of its connectivity, we find that the PCH finally has all its SATA connectivity sticking to the SATA revision 3.0 (6 Gb/s), compared to some of its immediate predecessors having some SATA 6 Gb/s ports, and some SATA 3 Gb/s. The PCH having all SATA 6 Gb/s ports is a particularly big revelation, because users of this platform will be able to finally set up complex RAID configurations using SATA 6 Gb/s drives, such as RAID 5, 10, etc., which require more than two physical disks.
This purism doesn't extend to USB, sadly. It still has a combination of USB 3.0 SuperSpeed and USB 2.0 HiSpeed ports in an unknown proportion. All USB 3.0 ports backwards-support USB 2.0 devices, but then not all USB ports from this chipset are USB 3.0. The chipset also lacks a PCI Express 3.0 hub and retains PCI Express 2.0. This bit is significant, because now makers of third-party USB 3.0, Thunderbolt, and SATA 6 Gb/s are encouraged to make PCIe 2.0 x2 controllers instead of waiting to see if chipsets in the foreseeable future have PCIe 3.0, so they could make lower pin-count PCIe 3.0 x1 controllers.
The rest of the connectivity is largely similar, except of course the display output. The PCH now only has to deal with analog display outputs. Gigabit Ethernet MAC, SPI, LPCIO, SMBus and HD Audio are carried forward unchanged. Haswell and Lynx Point are slated for the first half of 2013.