Taiwan Semiconductor Manufacturing Company (TSMC) has announced the unveiling of the foundry's first 40nm manufacturing process technology with first wafers expected in the second quarter of 2008.
The new node supports a performance-driven general purpose (40G) technology and a power-efficient low power (40LP) technology. It features a full design service package and a design ecosystem that covers verified third-party intellectual property (IP), third-party electronic design automation (EDA) tools, TSMC-generated SPICE models and foundation IP, noted the foundry.
The new 40nm node features manufacturing innovations that enable its LP and G processes to deliver a 2.35 raw gate density improvement of the 65nm offering. The transition from 45nm to 40nm low-power technology reduces power scaling up to 15%, the company highlighted.
TSMC has developed 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including CPU, GPU, games console, networking and programmable gate array (FPGA) designs and other high-performance consumer devices. The 40nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242-micron squared.
A full range of mixed signal and RF options accompany the 40G and 40LP processes along with embedded DRAM, to match the breath of applications that can take advantage of the new node's size and performance combination.
The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. The logic family includes a low-power triple gate oxide (LPG) option to support high-performance wireless and portable applications. Both the G and the LP processes offer multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.
TSMC's CyberShuttle prototyping service can be booked for 40nm designs in April, June, August, October and December 2008 and first wave 45/40nm customers have already used above 200 blocks on completed multi-project wafer runs. The 40G and LP processes will initially run in TSMC's 12-inch wafer Fab 12 and will be transferred to Fab 14 as demand ramps.